The present invention relates to a technique of measuring a dimension of a semiconductor device, for example, a dimension of a gate electrode on an activation region.
Recently, the size of a semiconductor device is becoming more miniaturized, and the dimension accuracy is required more strictly so that a gate electrode of 0.1 μm or less should be processed to have the dimensional accuracy of 10% or less. For example, the size of a gate electrode is one of main factors that determine operating characteristics of a semiconductor device, and it is particularly necessary to control the dimension of a gate electrode on an activation region. In manufacturing process, the dimension of a gate electrode varies being affected not only by a gate electrode fabrication process but also by the film thickness of the gate electrode and processes performed before the gate electrode fabrication process, such as a process affecting the dimension of a resist pattern used as a mask at the time of the processing of the gate electrode. As a result, even if a gate electrode is fabricated according to the same fabrication process under the same processing conditions, the finished dimension of the fabricated gate electrode does not become a constant value owing to accumulation of minute variations in those processes. For example, for the target value of 90 nm of a finished dimension of a fabricated gate electrode, there arises variation of the finished dimension in the range of about 10 nm at 3σ. This will cause worsening of dimensional accuracy, and eventually productivity will be lowered. Thus, control of a gate electrode dimension is indispensable technique in manufacturing process of a semiconductor device.
In manufacturing process of a semiconductor device, dimensions of gate electrodes in a wafer are measured. When measuring results miss a control value, the wafer is discarded or subjected to, for example, reprocessing in order to improve the yield and productivity. Recently, introduction of process control using such measured values is promoted. For example, Patent Document 1 shows a method of modifying processing conditions of control processes. In the method disclosed in Patent Document 1, a first process is performed on a semiconductor wafer to acquire integrated measured data relating to the process, and then, at least one error is specified from the integrated measured data, and an adjustment process for a second process is performed in order to compensate the error.
Another example is shown in Patent Document 2. Patent Document 2 includes a step in which a work-piece is processed and a step in which a transistor model is used for outputting feature parameters from measured feature parameters. Further, the method disclosed in the Patent Document 2 uses a step in which the output step is used to predict a wafer electrical test, a step in which a defective process is detected on the basis of the predicted values, and a step in which the defective process is corrected. Further, Patent Document 3 describes a method in which a dimension of an element isolation region is controlled by feed-forward. Patent Document 3 discloses a method in which a model formula for a surface step between an element isolation region and an activation region is generated. The model formula based on data of film thickness measured after Chemical Mechanical Polishing (CMP) is used for controlling the surface step to be constant by controlling the length of time of a cleaning process for removing a buried oxide film.
When such process control is performed, the accuracy of measurement results and improvement of throughput become important factors for the accuracy of the process control.
On the other hand, in recent lithographic techniques, the wavelength of a light source becomes shorter in order to cope with miniaturization of line-width, and, in association with this, resist material is changed. Particularly, as shown in Non-patent Document 1, line-width variation called Line Edge Roughness (LER) is obvious in the case of a resist material adapted for ArF excimer laser having the light source wavelength 193 nm (hereinafter, referred to as ArF resist). The variation of the line-width is about 6 nm at 3σ. Accordingly, in measuring a dimension of line-width, there is a problem that measurements of line-width at different places of the same line lead to different measurements. Thus, there is a problem that dimension measurement accuracy becomes worse in a dimensional inspection process of a semiconductor device manufacturing process using a resist pattern of a large LER. On the other hand, a method that can measure a minute pattern of line-width 0.1 μm or less with high accuracy and at a high speed is required.
Under these conditions, some methods of measuring line-width are proposed. One of them is a line-width measuring method using a Critical Dimension-Scanning Electron Microscope (CD-SEM), which is used most widely today. The characteristic of a CD-SEM is that it uses an electron beam so that it can obtain a high-resolution image even if line-width is 0.1 μm or less and it can measure any measuring object. Further, it is known that generally ArF resist shrinks by irradiation of an electron beam, and the shrinkage depends on the exposure dose. However, the latest model of CD-SEM has a function of automatizing measurement to reduce shrinkage to the minimum for each measuring object and a function (Rectangular Scan) of widening intervals of electron beam scanning to reduce the shrinkage. By changing electron beam scanning intervals, the Rectangular Scan function can obtain an image whose longitudinal magnification and lateral magnification are different from each other. This line-width measuring method using a CD-SEM is relatively fast, and can measure any measuring object with high accuracy. A CD-SEM performs processing in which a thus-obtained image of a wiring pattern is used for detecting many edge points of both ends of wiring on the basis of a contrast profile of the image and defines an average value of distances between edges as a dimension of the wiring. In this measurement, the longer the measured area is, the more the variation in measurements owing to LER can be reduced. Thus, the measuring method using a CD-SEM can measure an object with very high accuracy since it uses an electron beam.
As another method, there is a method using the scatterometry as shown in Non-patent Document 2. This method obtains optical interference waveform from patterns arranged to show a pitch over an area of 50 μm square or more. In this method, line-width is measured by comparing an interference waveform obtained by simulation using a structure model of the measuring object with an actually-obtained interference waveform. As a characteristic of this line-width measuring method using the scatterometry, it can relatively rapidly measure limited patterns such as the above-described ones that have simple structure for simulation and are arranged to show a pitch over an area of 50 μm square or more.
As another method, there is a line-width measuring method using a Critical Dimension-Atomic Force Microscope (CD-AFM) as shown in Non-patent Document 3. To measure a line-width, this method uses a minute probe to perform three-dimensional measurement of a measuring object directly. Since a measuring object is directly measured, the three-dimensional structure of the measuring object can be grasped. Further, its measurement accuracy largely depends on the size of a measuring object and the shape and dimension of the probe. Thus, as described above, there are a plurality of methods for measuring a line-width, and a suitable method is used depending on a purpose of measurement.
A measuring object used for dimension control is usually called a Quality Check (QC) pattern. In many cases, a QC pattern is arranged on a place called a scribe line, which is in a space between product chips and is to be cut by dicing. Further, in many cases, QC patterns are laid out to form a simple line or a plurality of lines/spaces for the sake of convenience of measurement. Actually, however, the performance and yield of a semiconductor device are determined by dimensions of wiring in operating circuit patterns, specifically dimensions of wiring on activation regions. A circuit pattern and a QC pattern are different from each other in complexity of their pattern shapes including lower layers, and thus different in behavior to dimensional variation. Thus, in dimensional control, the performance and yield of an actual semiconductor device can not be controlled sufficiently even if a dimension of a QC pattern is controlled. It is favorable to measure directly the dimension of a gate electrode of a circuit pattern. However, it is difficult to use measurement of a line-width of a specific place in a circuit for dimension control, since preparation of a measurement recipe is complicated and measurement accuracy of an individual point becomes lower because of the above-mentioned LER. Non-patent Document 4 describes a technique that can simply prepare a measurement recipe for dimension measurement in a circuit pattern. This technique uses design data to prepare a measurement recipe, and can measure a target place taking a plurality of layers into consideration. In other words, this technique can measure a line-width on an activation region.
Further, in many cases, a circuit pattern is formed such that activation regions and element isolation regions are arranged periodically. Non-patent Document 5 describes that, when there is such structure in a lower layer, dimensions of gate electrodes vary depending on that structure. This means that a dimension of a gate electrode on an activation region is different from a dimension on an element isolation region. Thus, when there is structure in a lower layer, an average dimension for the whole wiring is different from a dimension on an activation region. Also with respect to a resist pattern that becomes a mask for etching, it is confirmed that there is a phenomenon of variation in dimensions of wiring between on an activation region and on an element isolation region. Thus, as a wiring dimension that affects the performance and yield of a semiconductor device directly, it is necessary to measure a dimension on an activation region.
As described above, methods of measuring a minute measuring object with high accuracy have been proposed as follows.
Patent Document 1: Tokuhyo 2005-510083 (Published Japanese translation of published PCT application);
Patent Document 2: Tokuhyo 2003-531491 (Published Japanese translation of published PCT application);
Patent Document 3: Japanese Un-examined Patent Application Laid-Open No. 2002-151465;
Non-patent Document 1: A. Yamaguchi, et al., Proceedings of SPIE, vol. 5375, pp. 468-476 (2004);
Non-patent Document 2: B. Cheung et al., Proceedings of SPIE, vol. 5752, pp. 30-40 (2005);
Non-patent Document 3: V. A. Ukraintsev, et al., Proceedings of SPIE, vol. 5752, pp. 127-139 (2005);
Non-patent Document 4: C. Tabery, et al., Proceedings of SPIE, vol. 5752, pp. 1424-1434 (2005); and
Non-patent Document 5: M. Kurihara, et al., Proceedings of DPS, pp. 181-182 (2006);
As recent requests for processing accuracy become more rigid, it is more difficult to realize requested processing accuracy by simple improvement of individual processes. Thus, there is a method in which process control is performed so that a dimension as a control object is stabilized to be some standard value. Further, the performance and yield of a semiconductor product is determined not by a wiring dimension of a QC pattern but a wiring dimension of a circuit pattern, particularly on an activation region. Thus, it is necessary to measure a dimension on an activation region with high accuracy and at a high speed and to control the dimension of wiring.
Further, as a method of measuring a dimension of wiring, Non-patent Document 1 describes a method that uses a CD-SEM and an image of an area long in the length-wise direction of wiring. It is expected that this method will reduce variation in measurements owing to LER and be effective in improving measurement accuracy. Since, however, this method calculates, as a line-width, an average value over the whole measurement area, this method is not appropriate for calculation of a dimension only on an activation region. Further, this method employs image recognition in order to specify a target place of measurement, and this becomes one factor causing reduction of throughput of measurement.
As another measuring method, Non-patent Document 2 describes a measuring method using the scatterometry. This method can measure at a high speed. However, this method can measure only an average dimension in an area of 50 μm square, and thus is not sufficient for calculation of a dimension on an activation region.
Further, as another measuring method, Non-patent Document 3 describes a method using an AFM. This method is effective in obtaining a three-dimensional image of a pattern to be measured. However, since it takes a long time for measuring one point and there is no mechanism for extracting a dimension on an activation region, the method is insufficient to be used for an apparatus for inspecting a dimension of wiring in manufacturing process of a semiconductor device.
Further, as another measuring method, Non-patent Document 4 describes a method using a CD-SEM for measuring a dimension of wiring on an activation region. Since this method uses design data, it is possible to measure a dimension of wiring on any activation region in a circuit pattern. Further, to specify a measurement value on an activation region, a pattern layout generated from design data is compared with a pattern obtained from an actual SEM image, and a place to be measured is specified by image recognition. However, this method shows variation in measurements owing to the above-mentioned LER, and thus, measurement accuracy for each point is lower. Further, although it is possible to reduce variation in measurements owing to LER by increasing the number of points to be measured, the length of time required for measuring one point becomes longer since points to be measured are specified by image recognition. Thus, throughput of the method is insufficient to be applied to a wiring dimension inspection process.
In summary, to improve the performance and yield of a semiconductor device, a means of measuring a dimension on an activation region of a circuit pattern is required, and further, a method of managing and controlling the measured dimension is required. The conventional techniques are, however, insufficient to measure a dimension of wiring on an activation region with high accuracy and at a high speed.
Usually, a pattern to be measured at the time of control of dimension exists between semiconductor chips, and a QC pattern positioned at a part to be cut by dicing is measured. A QC pattern has a relatively simple layout for the sake of easiness of measurement. In dimension control, a dimension of such a simple layout is measured to examine whether an abnormal value or the like exists. Further, also in process control, measured data of a QC pattern is used. However, in comparison with a layout of a QC pattern, a layout of an actually-operating circuit pattern has a very complicated shape including not only a gate electrode but also lower layers of element isolation regions and the like. As a result, behavior of a dimension of a circuit pattern and behavior of a dimension of a QC pattern, i.e. behaviors such as variations in a wafer surface or variations between wafers or lots, do not necessarily coincide with each other. It is improvement in device characteristics and improvement in yield that is important in manufacturing of a semiconductor device. Further, those improvements are directly affected not by a dimension of a QC pattern but by a dimension of a circuit pattern. Particularly, it is essential to control accurately a dimension of a gate pattern on an activation region. Further, it is considered to place a circuit pattern on a scribe line to treat the pattern as a QC pattern and to control its dimension. However, a layout of a circuit pattern is complicated and thus it is difficult to measure such a circuit pattern with high accuracy. Further, in the case of measurement of a dimension of a gate electrode over an activation region in a circuit pattern, it is complicated to prepare a measurement recipe for a measuring apparatus, and variation in measurements owing to LER lowers the measurement accuracy. For these two reasons, it is difficult to introduce dimension control of a circuit pattern into an actual production line.
As shown in Non-patent document 4, as a means of measuring a dimension of a gate electrode on an activation region in a circuit pattern, there is a method of preparing a measurement recipe for a measuring apparatus on the basis of design data. This method uses not only a layout of a gate electrode but also design data of lower layers. As a result, it is possible to prepare easily a measurement recipe for measuring a dimension on an activation region at any place in a circuit pattern. However, even if this method is employed, accuracy of measured data of each individual point is lower because of variation owing to LER. It is considered to increase the number of points to be measured and to take an average value of them, to reduce measurement deviation. However, it can not be said that this is a good method since there is a trade-off relationship between the number of points to be measured and the throughput of measurement. As seen from the above, stable production of a semiconductor device needs a method of designing an easily-measurable QC pattern whose behavior is equal to a circuit pattern and a method of measuring a dimension on an activation region of that QC pattern with high accuracy and at a high speed.
The present invention has been made to solve the above problems. An object of the present invention is to provide a technique to measure a specific part of a semiconductor device with high accuracy and at a high speed.